With the increase in high integration degree of semiconductor devices, multi-layer interconnection technologies are increasingly required.
To secure a photolithography process margin and minimize a length of interconnection in such multi-layer interconnection technologies, an insulating layer and a conductive layer which are formed on a semiconductor substrate should be planarized. If they are not planarized, interconnections may be frequently made open or short due to serious topology.
For this reason much effort has been dedicated to planarizing the insulating and conductive layers to form a contact plug.
FIGS. 1a through 1d show process steps of a prior art method for forming contact plugs. Referring to FIG. 1a, a gate electrode 4, for example, a word line of a semiconductor memory device is formed on a semiconductor substrate 1 in which a device isolation layer 2 is formed. An insulating layer 6 of oxide is deposited over the semiconductor substrate 1 including the gate electrode 4. The oxide layer 6 has an uneven surface following the topology of the gate electrode 4. Also, two regions having a step with each other are generated on the insulating layer 6, one of which is a high-step region where the gate electrode 4 is formed, and the other of which is a low-step region wherein the gate electrode is not formed.
Next, when an etching of the insulating layer 6 having the uneven surface is performed using a CMP (chemical mechanical polishing) process, the upper surface of the insulating layer 6 can be planarized as shown in FIG. 1b.
With reference to FIG. 1c, the planarized insulating layer 6 is also etched until a diffusion region (not shown) on the semiconductor substrate 1 is exposed, and thereby a contact hole 8 is formed. Subsequently, a conductive layer 10 of, for example, polysilicon is deposited on the insulating layer 6 filling up the contact hole 8.
Finally, as shown in FIG. 1d, a CMP process is performed to etch the conductive layer 10 until the upper surface of the insulating layer 6 is exposed, and thereby a contact plug 10a of polysilicon is formed.
Herein, we should give attention to the fact that in the prior art method the CMP process of the insulating layer 6 is first performed before the formation of the contact plug 10a, and thereby a scratch is generated on the insulating layer 6 during the CMP process. This scratch on the insulating layer 6 may lead to a bridge between interconnections to be formed on the contact plug when a conductive material is formed in the scratch. Also, the insulating layer 6 should be deposited enough to cover the gate electrode 4 and assure surface planarization of the insulating layer. Thus, a sufficient time is required for the planarization/etching of the insulating layer. This leads to decrease in a fabrication yield of semiconductor devices.
In brief, the prior art method for forming contact plugs leads to two problems: first, microscrach and pitting on the insulating layer 6 are generated due to polishing during CMP process thereof. This problem may cause a bridge to form between interconnections to be formed by a following metallization. Second, a thickness of an insulating layer for planarization becomes more difficult to be reduced. As a result of these problems the fabrication process may have a decrease in reliability and yield.